What it sells
Lightning fast chips with hardcoded AI models
Business model breakdown
Workflow: what inputs become what output?
Compile a whole model, weights included, into silicon (MPU); today ships Larry, a 1-bit Qwen 27B (3.8 GB), an FPGA accelerator on a Kria KV260 board, and an RL chip-design environment.
Economics: what it saves and how it charges
Pre-revenue hardware/model R&D; goal 20,000+ tokens/s via hardcoded-model chips; custom ASIC design offered ("Build this chip").
Distribution: how it reaches customers
Contact by email; live web demos (Larry) for lead generation; no sales process published.
Funding history and coverage
| Round date | Stage | Amount | Investors | Source |
|---|---|---|---|---|
| — | Y Combinator Summer 2026 | — | Y Combinator | ycombinator.com |
Profiles summarize public reporting and company websites. Business-model notes are MaxBC's reading of that material, not confirmed facts; unknowns are left blank rather than guessed. Updated 2026-10-12.